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SY87813L
3.3V, 28Mbps to 1.3Gbps AnyRate(R) Clock and Data Recovery
General Description
The SY87813L is a complete clock recovery and data retiming integrated circuit for data rates from 28Mbps up to 1.3Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87813L also includes a link fault detection circuit. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
AnyRate(R)
Features
* 3.3V power supply * SONET/SDH/ATM compatible * Clock and data recovery from 28Mbps up to 1.3Gbps NRZ data stream; clock generation from 28MHz to 1.3GHz * Two on-chip PLLs: one for clock generation and another for clock recovery * Selectable reference frequencies * Differential PECL high-speed serial I/O * Line receiver input: no external buffering needed * Link fault indication * 100K ECL-compatible I/O * Industrial temperature range (-40C to +85C) * Available in 32-pin EPAD-TQFP
Applications
* * * * * SONET/SDH/ATM OC-1 and OC-3, OC-12, OC-24 Fibre Channel, ESCON, SMPTE 259 Gigabit Ethernet/Fast Ethernet Proprietary architecture up to 1.3Gbps CEPT E-3/E-4/E-5
Markets
* Telecom/Datacom * Fiber optics * Storage networks
AnyRate is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
November 2006
M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Ordering Information(1)
Part Number SY87813LHG SY87813LHGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type H32-1 H32-1
Operating Range Industrial Industrial
Package Marking SY87813LHG with Pb-Free bar-line indicator SY87813LHG with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin EPAD-TQFP (H32-1)
November 2006
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M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Pin Description
Pin Number 1 2 3 Pin Name REFCLKSEL RDINP, RDINN Pin Name REFCLK Select (TTL Input). This input selects the single-ended TTL REFCLK input or the differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs. Serial Data Input. Differential PECL: These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight frequency ranges depending upon the state of the FREQSEL pins. See "Frequency Selection" Table. Frequency Select. TTL Inputs: These inputs select the output clock frequency range as shown in the "Frequency Selection" Table. Reference Clock. (Input): These inputs are used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin Carrier Detect. PECL Input: This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock frequency generated from REFCLK. No connect. Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL. Analog Ground. Ground. Ground pin and exposed pad must be connected to the same ground plane. Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL. Clock Select. TTL Input: This input is used to select either the recovered clock of the receiver PLL (TCLKSEL = HIGH) or the clock of the frequency synthesizer (TCLKSEL = LOW) to the TCLK outputs. Clock Output (Differential PECL): The PECL 100k outputs represent either the recovered clock (TCLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (TCLKSEL = LOW). These outputs must be terminated with 50 to VCC-2V or equivalent. This applies even if these outputs are not used. Output Supply Voltage. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible.(1) Clock Output (Differential PECL): These PECL 100k outputs represent the recovered clock used to sample the recovered data (RDOUT). Receive Data Output (Differential PECL): These PECL 100k outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. These outputs must be terminated with 50 to VCC-2V or equivalent. This applies even if these outputs are not used. Divider Select. TTL Inputs: These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" Table.
4 6 7 5 28 29 26
FREQSEL1 FREQSEL2 FREQSEL3 REFCLK, REFCLKP, REFCLKN CD
8 9 10 11 12, 13 15 14 16
NC PLLSP PLLSN GNDA GND PLLRP PLLRN TCLKSEL
18 17
TCLKP, TCLKN
19, 22 21 20 24 23
VCCO RCLKP, RCLKN RDOUTP RDOUTN
32 25
Note:
DIVSEL1 DIVSEL2
1. VCC, VCCA, VCCO must be the same value.
November 2006
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Micrel, Inc.
SY87813L
Pin Description (continued)
Pin Number 27 30 31 Pin Name VCC VCCA LFIN Pin Name Supply Voltage. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible.(1) Analog Supply Voltage. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible.(1) Link Fault Indicator (TTL Output): This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (900ppm).
Note: 1. VCC, VCCA, VCCO must be the same value.
November 2006
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M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................... -0.5V to +4.0V Input Voltage (VIN) ........................................... -0.5V to VCC Output Current (IOUT) Continuous........................................................ 50mA Surge .............................................................. 100mA Lead Temperature (soldering, 20sec.) ................... +260C Storage Temperature (Ts) ........................-65C to +150C
Operating Ratings(2)
Input Voltage (VCC)............................ +3.15V to +3.45V Ambient Temperature (TA) ................... -40C to +85C Junction Thermal Resistance(3) EPAD-TQFP (JA) 0lfpm airflow........................................ 27.6C/W 200lfpm airflow.................................... 22.6C/W 500lfpm airflow.................................... 20.7C/W
DC Electrical Characteristics
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Condition Min 3.15 Typ 3.3 120 Max 3.45 165 Units V mA
PECL 100K DC Electrical Characteristics(4)
VCC = VCCO = VCCA = 3.3V 5%; RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL VOH VOL VOSW IIL Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Voltage Swing Input LOW Current VIN = VIL (Min) Condition Min VCC-1.165 VCC-1.810 VCC-1.085 VCC-1.830 600 0.5 750 Typ Max VCC-0.880 VCC-1.475 VCC-0.880 VCC-1.620 900 Units V V V V mV A
TTL DC Electrical Characteristics(4)
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL VOH VOL IIH IIL IOS
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input LOW Current Output Short-Circuit Current
Condition
Min 2.0
Typ
Max VCC 0.8
Units V V V V A A A mA
IOH = -0.4mA IOL = 4mA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. VOUT = 0V, (Max., 1 sec.)
2.0 0.5 -175 +100 -300 -15 -100
November 2006
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Micrel, Inc.
SY87813L
AC Electrical Characteristics
VCC = VCCO = VCCA = 3.3V 5%; RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise noted.
Symbol fVCO fVCO tACQ tCPWH tCPWL tIRFT tIRFP Parameter VCO Center Frequency VCO Center Frequency Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW REFCLK TTL Input Rise Time REFCLKN, REFCLKP PECL Input Rise/Fall Time (20% to 80%) Output Duty Cycle (RCLK/TCLK) PECL Output Rise/Fall Time (20% to 80%) Recovered Clock Skew Data Valid Data Hold 45 100 -200 1/(2xfRCLK) -200 1/(2xfRCLK) -200 3 3 0.5 2 1.0 Condition fREFCLK x Byte Rate Nominal Min 650 5 15 Typ Max 1300 Units MHz % s ns ns ns ns
tODC tr, tf tSKEW tDV tDH
55 400 +200
% of UI ps ps ps ps
Timing Waveforms
November 2006
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M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Functional Block
Functional Description
Clock Recovery Clock recovery, as shown in the block diagram, generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by a filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency, stability, without incoming data, is guaranteed by an alternate reference input (REFCLK or REFCLKP/N) that the PLL locks onto when data is lost. If the frequency of the incoming signal varies by greater than approximately 900ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. Lock Detect The SY87813L contains a link fault indication circuit, which monitors the integrity of the serial data inputs. If the recovered serial data from RDIN is at the correct data rate (within 900ppm of the synthesizer frequency), the Link Fault Indicator (LFIN) output will then be asserted HIGH indicating an in-lock condition and will remain HIGH as long as this condition is met. In the event that the recovered serial data is not at the correct data rate (greater than 900ppm difference from the synthesizer frequency), then LFIN output will go LOW indicating an out-of-lock condition. This condition will force the Clock and Data Recovery PLL (CDR) to lock onto the synthesizer frequency until it is within the correct frequency range (less than 900ppm difference from the synthesizer frequency). Once the CDR is within the correct frequency range, it will again lock onto the RDIN input.
November 2006
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M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Frequency Selection Table(1)
FREQSEL1 0 0 0 0 1 1 1 1
Note: 1. SY87813L operates from 28MHz to 1300MHz.
FREQSEL2 0 0 1 1 0 0 1 1
FREQSEL3 0 1 0 1 0 1 0 1
fVCO/fRCLK 1 2 4 6 8 12 16 24
fRCLK (MHz) 650 - 1300 325 - 650 163 - 325 109 - 216 82 - 162 55 - 108 41 - 81 28 - 54
Reference Frequency Selection
DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20
Loop Filter Components(2)
R5 = 350 C3 = 1.0F (X7R Dielectric)
R6 = 680 C4 = 1.0F (X7R Dielectric)
Note: 2. Suggested values. Values may vary for different applications.
November 2006
8
M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Application Example AC-Coupled I/O
November 2006
9
M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Application Example DC-Coupled I/O
Related Product and Support Documentation
Part Number SY87701AL HBW Solutions Function 3.3V, 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery New Products and Applications
(R)
Data Sheet Link www.micrel.com/product-info/products/sy87701al.shtml www.micrel.com/product-info/products/solutions.shtml
November 2006
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M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Bill of Materials (AC-Coupled)
Item C6 C7 C10, C11 C12-C15, C18, C19, C27, C28 C20-C26 D1 D2 J2, J3, J4, J6 J5 Q1 R1 R2 R3-R10 R11-R16, R28-R30, R32 R21 R22 R23, R24 R25, R26 R27 R31 SMA1SMA10 SP1-SP6 SW1 U1 U2
Notes: 1. 2. 3. 4. 5. 6. 7. Vishay: www.vishay.com. Panasonic: www.panasonic.com. Johnson Components: www.johnson-components.com. Murata: www.murata.com. NTE: www.nte.com. CTS: www.cts.com. Micrel, Inc: www.micrel.com.
Part Number 293D685X0025B2T VJ206Y103JXJAT VJ0603Y105JXJAT VJ0402Y104JXJAT
Manufacturer Vishay Vishay
(1) (1)
Description 6.8F, 25V, Tantalum Capacitor, Size B 0.01F Ceramic Capacitor, Size 1206, X7R Dielectric 1.0F Ceramic Capacitor, Size 0603, X7R Dielectric 0.1F Ceramic Capacitor, Size 0402, X7R Dielectric
Qty. 1 1 2 8
Vishay(1) Vishay(1)
VJ0402Y104JXJAT P301-ND P300-ND/P301-ND 111-0702-001 BLM21A102F 459-2598-5-ND CRCW04023500F CRCW04026800F CRCW04021001F CRCW04021820F
Vishay(1) Panasonic Vishay(1) Johnson Components(3) Murata(4) NTE(5) Vishay(1) Vishay Vishay
(1) (1) (2)
0.01F Ceramic Capacitor, Size 0402, X7R Dielectric LED Diode, T-1 3/4, Red Clear T-1 3/4, Red LED Red, Insulated Thumb Nut Binding Post (Jumped Together) Black, Insulated Thumb Nut Binding Post, GND (Jumped to VEE) 2N2222A Buffer/Driver Transistor, NPN 350 Resistor, 2%, Size 0402 680 Resistor, 2%, Size 0402 1k Pull-up Resistor, 2%, Size 0402 182 Resistor, 2%, Size 0402
7 1 1 4 1 1 1 1 8 10
Vishay(1)
CRCW06031300F CRCW04021820F CRCW04021300F CRCW04022825F CRCW0402OOR0F CRCW04025000F 142-0701-851
Vishay(1) Vishay
(1) (1)
130 Resistor, 2%, Size 0603 12.1k Resistor, 2%, Size 0402 130 Resistor, 2%, Size 0402 82 Resistor, 2%, Size 0402 0 Resistor, 2%, Size 0402 50 Resistor, 2%, Size 0402 End Launch SMA Jack Solder Jump Option
1 1 2 2 1 1 10 6 1 1 1
Vishay Vishay Vishay
Vishay(1)
(1) (1)
Johnson Components(3) CTS
(6)
CT2068-ND SY87813L SY89322V
8-Position, Top Actuated Slide Dip Switch Low-Power 3.3V 28Mbps to 1300Mbps AnyRate(R) Clock and Data Recovery 3.3/5V Dual LVTTL/LVCMOS-to-Differential LVPECL Translator
Micrel, Inc.(7) Micrel, Inc.(7)
November 2006
11
M9999-112806-B hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87813L
Bill of Materials (DC-Coupled)
Item C6 C7 C10, C11 C12-C15, C18, C19, C27, C28, C29 C20-C26 D1 D2 J2, J3, J4, J6 J5 Q1 R1 R2 R3-R10 R15, R16, R30, R32 R21 R22 R23, R24 R27 R31 SMA1SMA10 SP1-SP6 SW1 U1 U2
Notes: 5. 6. 7. 8. 5. 6. 7. Vishay: www.vishay.com. Panasonic: www.panasonic.com. Johnson Components: www.johnson-components.com. Murata: www.murata.com. NTE: www.nte.com. CTS: www.cts.com. Micrel, Inc: www.micrel.com.
Part Number 293D685X0025B2T VJ206Y103JXJAT VJ0603Y105JXJAT VJ0402Y104JXJAT
Manufacturer Vishay Vishay
(1) (1)
Description 6.8F, 25V, Tantalum Capacitor, Size B 0.01F Ceramic Capacitor, Size 1206, X7R Dielectric 1.0F Ceramic Capacitor, Size 0603, X7R Dielectric 0.1F Ceramic Capacitor, Size 0402, X7R Dielectric
Qty. 1 1 2 8
Vishay(1) Vishay(1)
VJ0402Y104JXJAT P301-ND P300-ND/P301-ND 111-0702-001 BLM21A102F 459-2598-5-ND CRCW04023500F CRCW04026800F CRCW04021001F CRCW04021820F CRCW06031300F CRCW04021820F CRCW04022825F CRCW0402OOR0F CRCW04025000F 142-0701-851
Vishay(1) Panasonic Vishay
(1) (2)
0.01F Ceramic Capacitor, Size 0402, X7R Dielectric LED Diode, T-1 3/4, Red Clear T-1 3/4, Red LED Red, Insulated Thumb Nut Binding Post (Jumped Together) Black, Insulated Thumb Nut Binding Post, GND (Jumped to VEE) 2N2222A Buffer/Driver Transistor, NPN 350 Resistor, 2%, Size 0402 680 Resistor, 2%, Size 0402 1k Pull-up Resistor, 2%, Size 0402 182 Resistor, 2%, Size 0402 130 Resistor, 2%, Size 0603 12.1k Resistor, 2%, Size 0402 82 Resistor, 2%, Size 0402 0 Resistor, 2%, Size 0402 50 Resistor, 2%, Size 0402 End Launch SMA Jack Solder Jump Option
7 1 1 4 1 1 1 1 8 10 1 1 2 1 1 10 6 1
Johnson Components(3) Johnson Components(3) NTE(5) Vishay Vishay
(1) (1)
Vishay(1) Vishay(1) Vishay(1) Vishay
(1) (1)
Vishay Vishay
Vishay(1)
(1)
Johnson Components(3) CTS
(6) (7)
CT2068-ND SY87813L SY89322V
8-Position, Top Actuated Slide Dip Switch Low-Power 3.3V 28Mbps to 1300Mbps AnyRate Clock and Data Recovery
(R)
Micrel, Inc.
1 1
Micrel, Inc.(7)
3.3/5V Dual LVTTL/LVCMOS-to-Differential LVPECL Translator
November 2006
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Micrel, Inc.
SY87813L
6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically has more jitter) crystal-based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1k resistor to VEE.
Appendix A
Layout and General Suggestions 1. 2. 3. 4. Establish controlled impedance stripline, microstrip, or coplanar construction techniques. Signal paths should have approximately the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within 10ps. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network.
7.
8.
5.
November 2006
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Micrel, Inc.
SY87813L
Package Information
32-Pin EPAD-TQFP (Die Up) (H32-1)
November 2006
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Micrel, Inc.
SY87813L
PCB Thermal Consideration for 32-Pin EPAD-TQFP
Package Notes: 1. 2. Package meets Leve 2 moisture sensitivity classification and is shipped in dry-pack form. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
November 2006
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